The present invention relates to a semiconductor device having a multilayer wiring structure using copper and a method for manufacturing the semiconductor device.
Recently a semiconductor device with a dual-damascene structure has been provided in which copper wiring is employed as a multilayer-wiring layer.
FIGS. 22 to 26 are cross-sectional views each showing a prior art step of manufacturing a semiconductor device. A method for forming copper wiring in a dual-damascene structure will be described below with reference to FIGS. 22 to 26.
As shown in FIG. 22, a first wiring groove 62 is first formed in a first insulating film 61 and then a conductive film 63a such as a copper film is formed on the first insulating film 61 by electrolytic plating, with the result that the first wiring groove 62 is filled with the conductive film 63a. The conductive film 63a is flattened by CMP (Chemical Mechanical Polishing) and the surface of the first insulating film 61 is exposed. Consequently, a first wiring layer 63 is formed in the first insulating film 61.
As illustrated in FIG. 23, a second insulating film 64 is formed on the first insulating film 61 and the first wiring layer 63. A via hole 65 and a second wiring groove 66 are formed in the second insulating film 64 by lithography and dry etching.
Referring to FIG. 24, a barrier metal layer 67 having a thickness of 200 Å is formed on the second insulating film 64 and the first wiring layer 63, and a metal seed layer (not shown) having a thickness of 400 Å is formed on the barrier metal layer 67. Then, a conductive film 68 is formed on the metal seed layer by electrolytic plating, and the via hole 65 and second wiring groove 66 are filled with the conductive film 68.
As shown in FIG. 25, the conductive film 68, metal seed layer, and barrier metal layer 67 are flattened by CMP to expose the surface of the second insulating film 64. As a result, a via section 69 and a second wiring layer 70 that are electrically connected to the first wiring 63 are formed.
However, the via hole 65 decreases in size in accordance with miniaturization of elements and thus the conductive film 68 cannot sufficiently be buried into the via hole 65 from top to bottom. As a result, a void 71 is formed in the via hole 65 to cause faulty electrical continuity between the first wiring 69 and the via section 69, as illustrated in FIG. 26. If the opening of the via section 69 is smaller than the second wiring layer 70, the conductive film 68 becomes more difficult to bury. The void 71 is therefore easily formed in the via hole 65 to make a problem of the faulty electrical continuity more serious.